The present invention relates in general to electronic circuits, and is particularly directed to new and improved multistage current mirror circuit architecture, that is configured to minimize transistor base current errors or offsets in a low voltage application such as, but not limited to, the coupling to a low voltage codec of a subscriber line interface circuit, having very high output impedance and minimum crosstalk.
System equipments of telecommunication service providers customarily contain what are known as subscriber line interface circuits or xe2x80x98SLICsxe2x80x99, to interface communication signals with the tip and ring leads of a wireline pair used to serve a relatively remote piece of subscriber communication equipment. In order that they may be interfaced with a variety of telecommunication circuits, including those providing codec functionality, present day SLICs must conform with a very demanding set of performance requirements, including accuracy, linearity, insensitivity to common mode signals, low noise, low power consumption, filtering, and ease of impedance matching programmability.
Through the use of differential voltage-based implementations, designers of integrated circuits used for digital communications, such as codecs and the like, are able to lower voltage supply rail requirements for their devices (e.g., from a power supply voltage of five volts down to three volts). As a result, the communication service provider now faces the problem that such low voltage restrictions may not provide sufficient voltage headroom to accommodate a low impedance-interface with existing SLICs (such as those designed to operate at a VCC supply rail of five volts).
This limited voltage headroom problem may be illustrated by considering the design and operation of a conventional current mirror architecture, such as that shown in FIG. 1, which is of the type employed in a subscriber line interface circuit, and operates with a customary VCC supply rail of five volts. In this conventional current mirror design, an input NPN transistor 10 has its base 11 coupled to a voltage reference VREF, and its emitter 12 coupled to receive an emitter current I12 or input current Iin, from a digital communication device, such as a codec.
The collector 13 of the input NPN transistor 10 is coupled in common to the collector 23 of a first current mirror input PNP transistor 20, and to the base 31 of a base current compensator PNP transistor 30; the collector 33 of which is coupled to a voltage reference terminal, such as ground (GND). The emitter 32 of the base current compensator PNP transistor 30 is coupled in common to the base 21 of the current mirror input transistor 20 and to the base 41 of a PNP current mirror output transistor 40. The emitters 22 and 42 of current mirror transistors 20 and 40 are respectively coupled through resistors 24 and 44 to a (VCC) voltage supply rail 16, while the collector 43 of the current mirror output transistor 40 is coupled to an output terminal 45, from which an output current IOut is derived.
Although working reasonably well when operating at a designed power supply rail voltage VCC of five volts, the current mirror of FIG. 1 lacks sufficient overhead for proper circuit operation, when interfaced with a circuit (such as a differential voltage-based codec) that operates at a much lower VCC rail value (e.g., on the order of only three volts and a reference voltage VREF of only half that value). In addition, although the mirrored output current Iout at the output node is first order compensated for PNP base current errors, it is not compensated for the NPN base current error in the input transistor.
More particularly, the mirrored output current Iout at the current mirror""s output terminal 45 corresponds to the collector current I43 flowing out of the collector 43 of the current mirror output transistor 40 which, for equal geometry current mirror input and output transistors, may be defined as:
Iout=I43=xcex1NPN10I12xe2x88x922I12/xcex2PNP2,
or
Iout=I12(xcex1NPN10xe2x88x922/xcex2PNP2).
Therefore, the value of the mirrored output current Iout may be approximated as:
Iout=Iin(1xe2x88x921/xcex2NPN).xe2x80x83xe2x80x83(1)
From equation (1), it can be seen that the mirrored output current Iout at the collector 43 of the current mirror output transistor 40 not only includes the desired input current Iin, but contains an undesired base current error component Iin/xcex2NPN associated with the NPN input transistor 10.
Due to the extremely tight voltage tolerances associated with the use of substantially lower VCC supply rail and reference VREF voltages, there is no available headroom in the collector-emitter current flow path through transistors 10-20 and the VCC supply rail for insertion of an NPN base current error compensating transistor.
As an alternative architecture, the input transistor 10 may be removed, with the input current Iin applied directly to the collector 23 of the current mirror input transistor 20. However, this does not resolve the base current error problem, since the overhead voltage at the circuit""s input port (the collector 23 of current mirror input transistor 20) is again two base-emitter diode voltage drops (Vbe20+Vbe30) below VCC.
For this alternative circuit implementation, the mirrored output current may be defined as:
Iout=Iin(1xe2x88x921/xcex2P2).xe2x80x83xe2x80x83(2)
In accordance with the invention described in the ""439 application, this base current error problem is successfully remedied by the current mirror circuit architecture shown in FIG. 2. This improved current mirror provides an overhead voltage that substantially reduces base current error, and offers a one base-emitter diode drop improvement over the overhead voltage of the conventional circuit. To this end, a bipolar PNP input current mirror transistor 50 of a current mirror input stage 200 has its base 51 coupled to the base 61 of a first bipolar PNP output current mirror transistor 60 of a first current mirror output stage 210-1 and to the base 71 of a second bipolar NPN output current mirror transistor 70 of a second current mirror output stage 210-2.
The respective emitters 52, 62 and 72 of the current mirror transistors 50, 60 and 70 are coupled (either directly of through resistors) to the power supply rail VCC. The first current mirror output transistor 60 of the first output stage 210-1 has its collector 63 coupled to a first current output port Iout_1, while the second current mirror output transistor 70 of the second output stage 210-2 has its collector 73 coupled to a second current output port Iout_2. The out put currents produced at the output currents Ioutxe2x80x941 and Ioutxe2x80x942 of respective output stages 210-1 and 210-2 are proportional to the geometry ratios of the output transistors 60 and 70 to the current mirror input transistor 50.
As in the conventional current mirror architecture of FIG. 1, the base 51 of the current mirror input transistor 50 is coupled to the emitter 82 of a base current compensator PNP transistor 80. However, rather than having its base 81 connected directly to the collector 53 of the current mirror input transistor 50, the base current compensator transistor 80 has its base coupled to the emitter 92 of an NPN base current error-reduction transistor 90. The NPN base current error-reduction transistor 90 and the base current compensator PNP transistor 80 form a buffer circuit between the current mirror and an input terminal Iin, to which the input current Iin is coupled.
The base current error-reduction NPN transistor 90 has its base 91 coupled to the collector 53 of transistor 50 of the current mirror input stage 200, and its collector 93 is coupled to the VCC supply rail. The emitter 92 of transistor 90 is further coupled to the collector 103 of an NPN transistor 100, the base 101 of which is coupled in common with the collector and base 111 of a diode-connected current mirror reference transistor 110 of auxiliary turn-on, pull down transistor pair.
The emitter 102 of NPN transistor 100 and the emitter 112 of NPN transistor 110 are coupled to ground (AGND). The collector 113 of transistor 110 is coupled to the collector 83 of base current compensator PNP transistor 80. In addition, a diode 120 has its anode 121 coupled to the emitter 92 of NPN base current error-reduction transistor 90 and its cathode 122 coupled to the input port Iin. Diode 120 serves to ensure that the circuit turns on in the presence of a slowly ramping power supply.
An examination of the circuit of FIG. 2, in particular the circuit path through the buffer circuit transistors 80 and 90, reveals that the installation of the NPN base current error-reduction transistor 90 results in an overhead voltage Vovrhd of:
Vovrhd=VCCxe2x88x92VbePNP50xe2x88x92VbePNP80+VbeNPN90.xe2x80x83xe2x80x83(3)
For equal geometries of like polarity devices, equation (3) may be rewritten as:
Vovrhd=VCCxe2x88x922VbeP+VbeN,xe2x80x83xe2x80x83(4)
which reveals at least a base-emitter diode drop larger than the overhead voltage of the conventional circuit of FIG. 1. This improvement in overhead voltage, although somewhat modest, may be of critical importance in reduced power supply rail applications (e.g., three volts or less). In addition to improving the overhead voltage, the circuit of FIG. 2 substantially reduces base current error.
Now, depending upon the application, a given current mirror architecture may be required to exhibit very large output impedances and very low power with minimal crosstalk. These requirements, when coupled with the constraint that the circuit operate at a reduced voltage supply, which may be an issue at both the input terminal and the output terminal of the current mirror, present a substantial challenge to the circuit designer.
Pursuant to the invention, this challenge is successfully addressed by an enhancement to the current mirror architecture of the above-referenced ""439 application, in which the emitter area of the input stage""s input current mirror transistor is used as a normalizing factor, and each output stage contains additional current circuitry that compensates for geometry differences of the respective current mirror and compensator transistors, so as to minimize crosstalk between the output stages, while dissipating minimal power. In addition, the emitter areas of transistors of the input stage are tailored in accordance with a set of current compensation relationships between the transistor circuits of the output stages and the input stage.
In order to take into account all of the current mirror drive transistors, the emitter area of the current mirror reference transistor of the auxiliary turn-on, pull down transistor pair is sized to be equal to the sum of the emitter areas of the current mirror input transistor of the current mirror input stage and all of the current mirror output transistors of the current mirror output stages. In addition, the transistor coupled in a current mirror configuration with the current mirror reference transistor has the same emitter area as the current mirror input transistor of the input stage.
Because the base current compensator PNP transistor of the current mirror s input stage""s conducts the sum of the base currents of current mirror input transistor and the current mirror output transistors of all of the current mirror output stages, its emitter current is proportional to a summation of the emitter area ratios of all the current mirror stages. Likewise, the emitter current through the current mirror reference transistor may be expressed as an emitter area ratio summation current. These relationships, coupled with the fact that the base current of the base current error-reduction transistor is equal to 1/xcex22 times the emitter current of the input stage""s current mirror transistor, make the emitter current of the input stage""s current mirror input transistor proportional to 1/xcex1 times the input current.
The current compensation circuitry of each output stage includes an additional current mirror transistor coupled in a current mirror configuration with the input stage""s reference transistor. This additional current mirror transistor has the. same emitter area as the current mirror output transistor of that stage. The current mirrored at the collector of this additional transistor is reproduced by a further current mirror circuit that is summed with the mirrored collector current of the output transistor and applied to the emitter of an output port-driving transistor. The resulting output current supplied to that stage""s output port is therefore equal to the summed current multiplied by the xcex1 of the output port-driving transistor.
The output port-driving transistor is coupled to a bias stage, that includes a pair of serially coupled, diode-connected transistors that provides a base bias of two base-emitter drops below VCC to the bases of the output port-driving transistors. The emitter-collector current flow path through these diode-connected transistors is coupled to a further transistor coupled in current mirror configuration with the reference transistor of the input stage. This further transistor has an emitter area equal to the emitter area of the reference transistor.